Description
The Vertical Summit 100 PRI Interface Board (VS-5135-00) features:
• Provides a standard PRI or E1R2 interface circuit
• May be installed on the MBU(CN2 & CN12)
• The interface circuit complies with ITU-T Recommendations G.704, G.703 and G.823
• Employs the CEPT frame format, which consist of 32, 8-bit time slots at a data rate of 2.048MHz
• The time slot TS 0 is allocated to frame alignment
• Tme slots:
— TS 0 is allocated to frame alignment
— TS 16 is allocated as the signaling channel
— 30 time slots are available as Bearer ‘B’ channels
• The PRIU circuit will extract the reference clock from the incoming PRI circuit
• The extracted clock is sent to the PLL circuitry of the MBU to synchronize the main clocks
• The PRIU can operate in the TE slave or NT master mode
• The PRIU supports:
— PULSE dialing
— DTMF dialing
— MFC-R2 register signaling (based on ITU-T Recommendation Q.440-480)
• Has a multiple pole Dip-switch to determine the type of interface circuit, PRI or E1R2
• The TE and NT operating mode is determined through database configuration
• Condition: New
• One Year Warranty